FIG. 3(a) is a structure of a general IC card system. This system comprises a card reader/writer 1, a lead wire 3 such as a set of twisted paired lines, an IC card 7 connected to such lead wire 3 at the electrodes 5 provided at the end part of lead wire 3 and a controller 9 which controls respective operations of the system. The controller 9 is also connected with a motor 11 for inserting or extracting IC card 7 and a relay or solenoid 13.
In the system of FIG. 3(a), lead wire 3 connecting between card reader/writer 1 and IC card 7 is 1 meter long or longer and noises generated from motor 11 and relay or solenoid 13 which is included in the mechanism of the system appear on lead wire 3. Since lead wire 3 is equivalently formed by inductors and capacitors as shown in FIG. 3(b), it resonates at a certain frequency and this resonant frequency becomes considerably lower in cases where lead wire 3 is comparatively long. Accordingly, as shown in FIG. 3(c), the noise applied to lead wire 3 becomes a considerable wide-band interference signal which changes in a ringing mode both in positive and negative directions at the input part of IC card 7, namely at the input part of serial communication interface (SCI). This interference signal is superimposed, for example, as shown in FIG. 4, on the data signal which is transmitted, for example, to IC card 7 from card reader/writer 1 through lead wire 3 and, thereby, it is probable that data is errorneously read in IC card 7.
Therefore, the error correcting circuit as shown in FIG. 5 has been provided as the signal input part of IC card 7. The circuit of FIG. 5 is formed by a data slicer 15, a data latch 17, a data shift register 19 and a majority gate 21.
In the circuit of FIG. 5, the input data is sliced, as shown in FIG. 6, with reference to the predetermined threshold value at data slicer 15 and thereby a rectangular wave signal corresponding to the input data, namely the sliced data is obtained. This sliced data is fed to data latch 17 and is latched therein using the data sample clock having a frequency about 8 to 16 times the transmission frequency of the input data. An output Q of data latch 17 is fed to data shift register 19 and is sequentially shifted also by the data sample clock. Data shift register 19 is formed, for example, by three stages of shift registers. Outputs Q.sub.0, Q.sub.1, Q.sub.2 of respective stages are fed to majority gate 21 and data generated corresponding to the majority rule of respective outputs is derived. As explained earlier, the error correcting circuit of the prior art has corrected data error to a certain degree by using the majority gate.
However, in case the high amplitude and wide-band noise elements N1 and N2 indicated in FIG. 6 are superimposed, for example, on the input data in the circuit of FIG. 5, the conventional error correcting circuit has a disadvantage that the output data error cannot be corrected sufficiently even though the data correction is made based on the majority rule.